1. Field of the Present Invention
The present invention generally relates to the field of data processing systems and more particularly to a data processing system in which transactions on a shared bus are delivered to selected targets on the bus.
2. History of Related Art
In the field of data processing systems, the use of standardized peripheral busses is well known. Among the more prevalent of such busses is the Peripheral Components Interface (PCI) bus as specified in the PCI Local Bus Specification Rev. 2.2 available from the PCI Special Interest Group 5440 SW Westgate Drive, Suite 217, Portland, Oreg. 97221. Devices connected to the PCI bus are all mapped into a common, shared address space. Any bus master or transaction initiator can access any target device simply by reading or writing the target""s portion of the shared address space. PCI transactions are said to be anonymous because target devices are unable to determine the initiator of a transaction. The shared, anonymous characteristics of PCI are generally desirable attributes for conventional PCI environments in which a CPU or set of CPUs is one of the bus agents and the computer system peripherals are the other bus agents.
Referring to FIG. 1, a data processing system 100 typical of the prior art is depicted. Data processing system 100 includes one or more processors 102 that are each connected to a system bus 103. Processors 102 can access a system memory 104 via the system bus 103. In addition, a bus bridge/bus arbiter 106 is connected between the system bus 103 and a peripheral bus 107. For purposes of this discussion, the peripheral bus 107 is typically compliant with Rev 2.2 of the PCI Local Bus specification. One or more peripheral device(s) or adapter(s) 108 are connected to the peripheral bus 107. Peripheral devices 108 may include any number of devices including, as examples, hard disk adapters, graphics adapters, audio adapters, and high-speed network adapters. The address space of bus 107 is divided among peripheral devices 108. Typically, each peripheral device 108 tied to peripheral bus 107 is able to xe2x80x9cseexe2x80x9d every transaction that occurs on the bus. More specifically, all devices 108 on bus 107 receive the same data, address, and control signals. Thus, bus 107 is referred to as a shared bus. In addition, transactions on bus 107 are anonymous because the data, address, and control signals of bus 107 typically do not include information indicating the device that originated the transaction.
While a shared and anonymous bus may be suitable for traditional microprocessor based designs, it may be undesirable in a PCI-based multiprocessor environment. For purposes of this disclosure, a PCI-based multiprocessing system refers to a computer system in which multiple CPUs are connected to a single PCI bus. In this environment, it may be desirable to isolate or secure selected processors from others. Additionally, it may be desirable in a multiprocessor system to enable xe2x80x9cprivate conversationsxe2x80x9d between processors or between one or more processors and selected peripherals. The shared address space and anonymous transactions of the currently implemented PCI standard prevents such private or secure transactions. It would, therefore, be highly desirable to implement a system and method for enabling individual devices on a common PCI bus to communicate privately such that others are effectively prevented from seeing the communication. It would be further desirable if the implemented system did not require modification of existing PCI compliant devices and did not require alteration or amendment of the PCI specification itself. It would be still further desirable if the implemented solution did not require complex or extensive modifications to existing hardware.
The problems identified above are in large part addressed by a system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be dynamically modified in the preferred embodiment and may be used to provide a unique 1-bit signal to each bus agent. The permission signal may indicate whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit. In an embodiment in which the bus is a PCI bus, the gating circuitry may receive a bus control signal such as the FRAME# signal and the GNT# signals for each bus agent. If the corresponding permission signal is inactive or de-asserted, thereby indicating a prohibited initiator/target pair, the FRAME# signal and perhaps the GNT# signal are isolated from the bus agent and the gating circuit maintains the bus agent""s FRAME# and GNT# pins at VCC thereby preventing the bus agent from recognizing a bus transaction.